U.S. Pat. No. 6,711,663 discloses a flash memory device. Data can be read from flash memory devices more or less as from any semi-conductor memory devices. Writing data is more complicated. Typically writing involves erasing a block of memory cells and subsequently programming pages of data to the erased block. Typically, erasing can be performed only collectively for an entire block, which therefore forms the unit of erasing in this case. Programming can usually be done in smaller units, by definition called pages.
Flash memory devices have the problem that they suffer from wear. Data blocks can be erased and programmed only a limited number of times before they wear out, after which they can no longer be used reliably. If blocks of a flash memory device for specific addresses would be erased and programmed far more often than others, the useful life of these blocks would limit the useful life of the flash memory device.
This problem has been addressed by using time-varying logical to physical address mapping. Mapping can be used to make it possible that a logical address that is used to access the flash memory can refer to locations in different physical blocks of the flash memory at different times. Thus, logical addresses for which frequent erasing and programming is needed can be remapped from time to time to different physical blocks, in order to avoid that the same physical block has to be erased and programmed each time when the logical block is erased and programmed (as used herein a “logical block” refers to the set of addresses that maps to the complete set of mappable addresses in a physical block, and optionally also loosely to the data stored in these locations).
Efficient logical to physical mapping requires a mapping table, which contains physical addresses stored according to the logical addresses to which they correspond. In principle such a mapping table has to be updated each time when a change in physical to logical address mapping is made. Conventionally, such a mapping table for a flash memory is stored in a RAM memory. On power up the mapping table is reconstructed from “tags” stored in the flash memory, which indicate for different physical memory regions (e.g. blocks) what their current logical address is.
U.S. Pat. No. 6,711,663 describes the use of a mapping table that is stored in the flash memory itself. U.S. Pat. No. 6,711,663 uses segment organized mapping. The memory is organized as a plurality of segments of blocks. A respective mapping table is provided for each segment, which translates logical addresses for the segment into physical addresses in the segment. The size of the segments is selected so that the size of each mapping table corresponds to a memory page, the unit of programming of the flash memory.
U.S. Pat. No. 6,711,663 provides a “memory update block” in each segment, for storing successive versions of the mapping table of the segment. The last programmed page of the memory update block is used as mapping table. Each time when the mapping table of the segment has been changed the updated mapping table is programmed in a next page of the memory update block. After each change a new page is used to store the mapping table until all pages of the memory update block have been programmed. When a next update of the memory table occurs after all pages have been programmed, the memory update block is erased and the new memory table is written into the first page of the erased block.
This approach has the advantage that on power up no time is needed to reconstruct the mapping table from tags. Instead the mapping table can be retrieved directly from the flash memory.
However, if an interruption, like disconnection from the power supply has occurred after erasing the memory update block and before programming of the first new mapping table, such a retrieval is impossible. In this case a time-consuming tag based reconstruction of the mapping is needed.